JURNAL INTERNASIONAL

journal of Theoritical and Apllied Information Technology

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Adnvanced Encryption Standart (AES) crytographic system are widely used in embedded systems to secure secret infomation. One of the most powerful sryptanalysis techniques against the cryptograhpic systems is the fault injection attacks. THe complexcity of cryptograpic systems is increasing which requires fast security attacks simulation againts fault injection attacks. The multi-level Electronic System Level approach isone promosing candidate that allwos models to reach higher simulation speed. It is know that the systemC Transaction Level Modeling (TLM) package simulates models 1000 times higher than classicial Register Transfer Level (RTL) simulators.
In this paper, we present a secure reconfigurable AES design against the fault injection attacks at the Electronic System Level. simulation results demonstrate that the simulation time is dependet of the fault detection schemes types. Moreover, The SystemC design is refined to RTL level. It is translated from SystemC description to a VHDL equivalent and implemented on Xilinix Virtex-5 FPGA. Experimental synthesiss results show that the secure reconfigurable AES design is very robust against fault injection attacks and the fault detection scheme information redundacy allows a trade-off between the hardware overhead and the security against fault injection attacks.

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Ketersediaan

JI03220012

004.0285 JATIT J JurnalInternasional

Perpus STMIK (Jurnal Internasional)

Tersedia

Informasi Detail

Judul Seri

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No. Panggil

004.0285 JATIT J JurnalInternasional

Penerbit

USA : JATIT., 2014

Deskripsi Fisik

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Bahasa

English

ISBN/ISSN

1992 8645

Klasifikasi

004.0285

Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

Volume 66 Nomor 2 Tahun 2014

Subjek

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Info Detail Spesifik

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Pernyataan Tanggungjawab

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Versi lain/terkait

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